The present invention relates to a semiconductor integrated circuit and particularly to a semiconductor integrated circuit using MOS transistors.
In recent years, high integration and low power consumption have been promoted in various kinds of semiconductor integrated circuits. In a semiconductor integrated circuit, there is a threshold voltage Vt for determining the on-off characteristic of an MOS transistor. The threshold voltage Vt must be lowered to improve drivability to thereby improve the operating speed of the circuit. Even in the case where the internal supply voltage Vdd of the circuit is lowered, the threshold voltage Vt needs to be set to be small in order to keep the operating speed high.
Lowering of the threshold voltage Vt, however, incurs a problem that the power consumption of the semiconductor integrated circuit increases greatly due to rapid increase of leakage current as described in 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 45-46.
To prevent this problem, there is proposed a semiconductor integrated circuit in which the substrate bias voltage is changed according to the operating mode, such as a stand-by mode, an active mode, or the like, to thereby control the threshold voltage of an MOS transistor, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 166-167, 1996.
On the other hand, there is a further proposal in which real and virtual power supply lines are provided so as to be linked by switching MOS transistors so that main circuits are supplied with power through the virtual power supply lines but the switching MOS transistors are turned off in the stand-by mode to prevent the main circuits from being supplied with power to thereby achieve reduction of power consumption, in IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, August 1995. Increase of the leakage current is, however, unavoidable for high-speed operation in the active mode even in the case where these background-art techniques are used.
FIGS. 24A and 24B show three stages of inverters as an example of background-art circuit. FIG. 24A shows an equivalent circuit configuration. FIG. 24B shows a specific circuit configuration. When, for example, node O1 is at an "L" level in the stand-by mode, node O3 is at an "L" level and nodes O2 and O4 are at an "H" level. In this case, with respect to the first and second stages of inverters, a leakage current flows through transistors Q1 and Q4. If the threshold voltage of the transistors is lowered, the leakage current increases greatly.
On the other hand, in accordance with JP-A-7-162288, there is a proposal in which time difference is provided between a signal supplied to an MOS transistor changed from OFF to ON and a signal supplied to an MOS transistor changed from ON to OFF so that the former signal is propagated earlier than the latter signal to thereby achieve high-speed operation without providing any change of the threshold voltage Vt. If the former signal is propagated earlier, it is, however, impossible to expect a greatly speeding-up effect as a whole because the latter signal is propagated later. The inventors' examination has proved that the speeding-up effect is about 10% at the best.
In each of the background-art semiconductor integrated circuits, as described above, there was a problem that the leakage current in the active mode increased when the operating speed of the circuit was improved or kept high even when the internal supply voltage Vdd was lowered.